1. Field
Example embodiments relate to Error Control Codes (ECC). Also, example embodiments relate to ECC apparatuses and methods that may control a number of storage elements, depending on an error level generated in a channel using an I-interleaved coding scheme, and may control ECC performance.
2. Description of Related Art
When error levels generated in a channel are different, an Error Control Code (ECC) structure optimized depending on an error level is generally embodied.
Specifically, when the error level generated in the channel is low, a desired level of performance may be realized by an ECC of a simple structure having a low error correction capability. However, when the error level generated in the channel is high, an ECC structure having a high error correction capability and high-level complexity is required to realize the desired level of performance.
Generally, as a coding scheme having a high interleaving level is used, an error correction capability is increased. However, complexity and latency are increased and a code rate is decreased. Also, as a coding scheme having a low interleaving level is used, the error correction capability is decreased. However, complexity and latency are decreased and the code rate is increased.
Accordingly, when the error level generated in the channel is high, the coding scheme having the high interleaving level may be generally used, and when the error level generated in the channel is low, the coding scheme having the low interleaving level may be generally used.
However, since an ECC calculation is performed using a high-level interleaved coding scheme regardless of the error level of the channel changed when an interleaving level is fixedly used while the error level generated in the channel is high, latency is unnecessarily increased when the error level of the channel is lowered. Also, since unnecessarily redundant data transmission is required, a ratio of an information amount to a total code length, that is, the code rate is unnecessarily lowered.
Also, several structures may be configured together in order to use an ECC structure using a low-level interleaved coding scheme when the error level generated in the channel is low, and to use an ECC structure using the high-level interleaved coding scheme when the error level generated in the channel is high. However, complexity of a circuit is increased in this case.
Also, it is well-known that a correction capability of a continuous bit error corresponding to a burst error is increased when an interleaved coding scheme is generally used.
Accordingly, an ECC apparatus and method which can control a number of storage elements depending on an error level generated in a channel using an I-interleaved coding scheme, and control ECC performance is required.